1. Field of the Invention:
This invention relates to a method of operating a semiconductor memory device, and more particularly to a method of operating a semiconductor memory device having a volatile memory means and a non-volatile memory means.
2. Description of the Prior Knowledge:
Semiconductor memory devices of the prior art include a mask ROM (Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory) and other types of non-volatile memory devices which can retain their storage contents even when the power is off, and a DRAM (Dynamic Random-Access Memory) and other volatile memory devices which lose their storage contents when the power is off.
Non-volatile memory devices, a mask ROM and EEPROM are capable of retaining stored data for a long period of time after the power is cut off. However, in the case of a mask ROM, data cannot be rewritten after it has been written in a wafer process. In the case of an EEPROM, data can be rewritten after it has been arranged in an apparatus, but the period for data write/erase is as long as 10 ms and there is a limit to the number of possible write/erase cycles, so these devices are not suitable to applications in which data is repeatedly rewritten. In the case of RAM, however, which is volatile memory, data rewrite time is less than 10 ns and there is no limit to the number of times data can be rewritten, but when the power source is cut off, all stored data is lost.
Recently, the inventor invented a multiple-use semiconductor memory device in which data can be rewritten rapidly, and stored data can be retained for a long period of time in the absence of power supply (U.S. Ser. No. 549,293 filed Jul. 6, 1990).
FIG. 3 shows such an improved semiconductor memory device. The semiconductor memory device of FIG. 3 has a DRAM section DM comprising one MOS transistor T1 and one capacitor C, and an EEPROM section EM comprising a floating gate transistor MT. The source 10 of the transistor T1 is connected to the accumulation node 3 of the capacitor C, and the drain 9 of the transistor MT is connected to the accumulation node 3 via a mode selector transistor T2 which functions as a switch means. The control gate 5 of the transistor MT is also connected to the accumulation node 3. The transistor T2 is switched on or off by applying a positive bias voltage V7 or a zero bias on the gate terminal (mode selector gate) 7.
FIG. 8 shows a cross sectional view of the device of FIG. 3 which is formed on a semiconductor substrate 20. As shown in FIG. 8, the source 2 and drain 9 of the transistor MT are diffused areas which are formed below the floating gate 4. Between the source 2 and the floating gate 4, a tunnel oxide film 4a is disposed. The gate electrode 6 of the transistor T1 is connected to a word line, and the drain 1 is connected to a bit line BL.
This semiconductor device operates as follows when the transistor T2 is off, i.e., when the mode selector gate 7 is zero biased.
(1) First, as shown in FIG. 4, the DRAM section DM is electrically isolated. When data is to be written into the DRAM section DM, a cell selector gate voltage Vsg is applied to the gate terminal 6 to turn on the transistor T1, and the power source voltage Vcc or zero bias is applied to the drain 1, as shown in the top row of FIG. 6A. In response to the above, the potential of the accumulation node 3 becomes Vcc or 0. That is, the data in the DRAM section DM becomes "1" or "0". The source 2 of the transistor MT is zero biased.
(2) When data is written into the EEPROM section EM, as shown in the middle row of FIG. 6A, first the gate terminal 6 and drain 1 of the transistor T1 are zero biased to disable the DRAM section DM, and the source 2 of the transistor MT is zero biased while the program voltage Vpp which is greater than the power source voltage Vcc is applied to the other electrode (plate electrode) terminal 8 of the capacitor C. Then, electrons accumulate in the floating gate 4 through the tunnel oxide film 4a regardless of whether the data in the DRAM section DM is "0" or "1", and the threshold value of the transistor T2 becomes high (erase state), as shown in the column "step 1" of FIG. 5. At this time, the charges of the accumulation node 3 of the capacitor C do not escape since the transistor T2 is in the off state, so the data stored in the DRAM section DM does not change when the EEPROM section EM goes to the erase state. However, the capacitance of the capacitor C must be designed sufficiently large compared to the gate capacitances C.sub.52 (capacitance between the control gate 5 and the source 2) and C.sub.5 (capacitance between the control gate 5 and the substrate) of the transistor MT.
Then, as shown in the bottom row of FIG. 6A, the potential of the source 2 of the transistor MT is made to the program voltage Vpp while the plate electrode 8 of the capacitor C is zero biased. The storage contents of the EEPROM section EM change corresponding to the data state "0" or "1" of the DRAM section DM. For the sake of explanation, the coupling ratio Rc of the transistor MT is defined by the following expression: ##EQU1## where C.sub.45 is the capacitance between the floating gate 4 and the control gate 5, C.sub.4 is the capacitance between the floating gate 4 and the substrate, and C.sub.42 is the capacitance between the floating gate 4 and the source 2. Then, the voltage applied to the tunnel oxide film 4a is:
(a) when the DRAM data is "0", V.sub.0 (=Rc.Vpp); or
(b) when the DRAM data is "1", V.sub.1 (=Rc(Vpp-Vcc)).
That is, when the DRAM data is "0", a voltage which is higher by EQU V=V.sub.0 -V.sub.1 =Rc.multidot.Vcc
than in the case when the DRAM data is "1" is applied to the tunnel oxide film 4a.
In the case of (a) (when the DRAM data is "0"), the electrons accumulated in the floating gate 4 are pulled toward the source 2 because the voltage applied to the tunnel oxide film 4a is high. As a result, even if the potential of the floating gate 4 becomes high and the transistor MT turns to the on state, the electrons do not flow to the drain 9 since the transistor T2 is in the off state. In this way, many electrons are pulled away and the threshold value of the transistor MT becomes low (write state).
In the case of (b) (when the DRAM data is "1"), electrons remain accumulated in the floating gate 4 since the voltage applied to the tunnel oxide film 4a is low. Therefore, the threshold value of the transistor MT remains high (erase state).
In this way, the storage contents of the EEPROM section EM can be set to a write state (low threshold value) or erase state (high threshold value) in accordance with "0" or "1" of the data contents of the DRAM section DM, while the data contents of the DRAM section DM are retained.
Next, the on state of the transistor T2, i.e., the state wherein a positive bias V7 is applied to the mode selection gate 7 will be described.
(3) As shown in the top row of FIG. 6B, the DRAM section DM operates in the same way as in the off state described above, by setting the source 2 of the transistor MT to the open state and zero biasing the plate terminal 8 of the capacitor C.
(4) When data is to be written into the EEPROM section EM, the drain 1 and cell selection gate terminal 6 of the transistor T1 are zero biased to disable the DRAM section DM, as shown in the bottom row in FIGS. 6B and 7, a bias V2 for transfer is applied to the source 2 of the transistor MT while the plate terminal 8 of the capacitor C is zero biased.
As in the case where the transistor T2 is in the off state, the storage contents of the EEPROM section EM can be set to the write state or the erase state in accordance with the DRAM data "0" or "1". As shown in the equivalent circuit of FIG. 7, the drain 9 of the transistor MT is connected to the accumulation node 3 of the capacitor C, so that the charge of the accumulation node 3 is lost during the write operation through the drain 9 of the transistor MT. That is, the DRAM data is not retained, and transferred to the EEPROM section EM.
In this way, the improved semiconductor memory device operates as a DRAM capable of continually rewriting data at high speed, and is able to transfer data from a DRAM section DM to an EEPROM section EM, and also to rewrite EEPROM data while retaining DRAM data. Furthermore, even when the power is off, this device can store data as an EEPROM over a long period of time, thus giving it a wide range of applicability.
The improved semiconductor memory device in the state in which data is written in the DRAM section DM while the transistor T2 is off has the equivalent circuit shown in FIG. 2. When data is to be written into the DRAM section DM, the voltage Vsg is applied to the gate terminal 6 to turn on the transistor T1. In this condition, the power source voltage Vcc or zero bias is applied to the drain 1 through the transistor T1, and the source 2 of the transistor MT is zero biased (the potential is 0 V). During the operation of the DRAM section DM, therefore, the potential difference between the control gate 5 and the source 2 of the transistor MT is the power source voltage Vcc at the maximum. The storage contents of the transistor MT is rewritten by the application of the program voltage Vpp which is greater than the power source voltage Vcc. Hence, the application of the power source voltage Vcc is not directly led to the rewriting of the storage contents of the transistor MT.
In such a semiconductor memory device, however, it has been found that, when the DRAM section DM is operated for a long period of time while retaining the data initially stored in the transistor MT (i.e., without rewriting the storage contents of the transistor MT), charges move through the tunnel oxide film 4a due to Fowler-Nordheim tunneling, to be gradually accumulated over a long span of time, resulting in that the storage contents initially stored in the transistor MT may be changed. In this way, the above-described method of operating the improved semiconductor memory device involves a problem in that the characteristics of retaining storage contents (read retention) is impaired.